AVS 46th International Symposium
    Flat Panel Displays Topical Conference Tuesday Sessions
       Session FP+OE+EM-TuA

Paper FP+OE+EM-TuA4
Reduced Process Complexity Organic Thin Film Transistors

Tuesday, October 26, 1999, 3:00 pm, Room 604

Session: Thin Film Transistor Materials and Devices
Presenter: H. Klauk, The Pennsylvania State University
Authors: H. Klauk, The Pennsylvania State University
D.J. Gundlach, The Pennsylvania State University
M. Bonse, The Pennsylvania State University
T.N. Jackson, The Pennsylvania State University
Correspondent: Click to Email
The performance of organic thin film transistors (TFTs) has improved dramatically over the past few years and recently, pentacene TFTs with carrier mobility of 0.6 cm@super 2@/V-s were demonstrated on glass substrates.@footnote 1@ The TFT device structure used in this earlier work required 4 material depositions and 4 lithography steps: one each for the gate, the gate dielectric, the source/drain contacts, and the pentacene active layer. Patterning of the pentacene layer is important to avoid leakage since pentacene TFTs often have large positive threshold voltage. We report here a simplified device structure for depletion-mode pentacene TFTs. Only 3 material depositions and 3 lithography steps are required and the same metal deposition is used for the gate electrode and the source/drain contacts. Gate-to-source and gate-to-drain overlap are not required, since the pentacene layer is normally conducting, thus allowing a drain current to flow at zero gate bias; devices are turned off by applying a positive gate bias. Palladium was used for the gate and source/drain metal, and low-temperature (80°C) ion-beam sputtered SiO@sub 2@ was used as the gate dielectric; both layers were patterned by lift-off. To pattern the pentacene active layer, a double-layer photoresist technique was used to create a reentrant profile over which the pentacene was deposited by evaporation. Upon deposition, the pentacene layer breaks over the resist profile, leaving isolated TFT areas. At a relatively low drain-source voltage of -20 V, devices have carrier mobility as large as 0.3 cm@super 2@/V-s, on/off current ratio near 10@super 5@, subthreshold slope as low as 0.9 V/decade, and threshold voltage between +10 V and +17 V. @FootnoteText@ @footnote 1@ Hagen Klauk, David J. Gundlach, Jonathan A. Nichols, and Thomas N. Jackson, "Pentacene Organic Thin-Film Transistors for Circuit and Display Applications," IEEE Transactions on Electron Devices, vol. 46, no. 6, June 1999.