AVS 45th International Symposium
    Surface Science Division Tuesday Sessions
       Session SS1-TuM

Paper SS1-TuM8
The Role of Dimer-Stacking-Fault Structures in Si(111) Etching

Tuesday, November 3, 1998, 10:40 am, Room 308

Session: Semiconductor Surface Structure
Presenter: M. Fouchier, University of North Carolina, Chapel Hill
Authors: M. Fouchier, University of North Carolina, Chapel Hill
J.J. Boland, University of North Carolina, Chapel Hill
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Etching of semiconductors continues to be important from both a fundamental and applied prospective. In this work, we investigated the etching of Si(111) by halogens using Scanning Tunneling Microscopy. It is known that Si(111) etching occurs preferably at steps but also within terraces. We showed that Dimer-Stacking-fault (DS) structures are formed during etching by Bromine at 900K. These structures result from the coalescence of vacancies on the surface.@footnote 1@ These vacancies are produced either thermally or by isolate etching events. These results suggest that DS structures are intermediates in the terrace etching process and that the dimer-rows bounding these structures serve as etch sites. @FootnoteText@ @footnote 1@Marc Fouchier and John J. Boland, Phys. Rev. B 57, 8997 (1998).