Planar type single electron transistor(SET) and SET memory are proposed and realized on the atomically flat @alpha@-Al@sub 2@O@sub 3@ substrate using a STM/AFM nanofabrication process. Using STM tip/AFM cantilever as a cathode, the surface of the titanium(Ti) metal which was on an atomically flat @alpha@-Al@sub 2@O@sub 3@ substrate is selectively oxidized to form a few tens of nanometer wide oxidized titanium(TiO@sub x@) line just under the tip. The surface roughness of the 2.5nm thick Ti metal is less than 0.15nm and retains the atomically flat condition. The surface roughness of TiO@sub x@ is also less than 0.15nm. The TiO@sub x@ works as an energy barrier for an electron, and the barrier height between Ti and TiO@sub x@ is 468meV. Therefore, the narrow TiO@sub x@ line could be used for the tunneling junction for SET. The size of the SET island is 8nm x 26nm square. The width, the thickness, and the length of the two tunnel junctions are 19nm, 2nm, and 26nm, respectively. The tunnel junction capacitance calculated from these structure parameters is C@sub t@=0.12aF. The gate electrode is set 964nm away from the island. The SET operates even at room temperature and shows the Coulomb oscillation with the periods of ~1.8V at the drain bias of -0.3V. At the different drain bias from -0.2V to -0.7V, the drain current shows the same oscillation periods of ~1.8V against the gate bias change. From this periods of Coulomb oscillation, the gate capacitance is estimated to be C@sub G@=0.1aF. Owing to the atomically flat @alpha@-Al@sub 2@O@sub 3@ substrate, the uniformity and reproducibility of the TiO@sub x@ line improves drastically, and it makes possible to fabricate the SET memory with complicated multi-tunnel junction structure.