| Pacific Rim Symposium on Surfaces, Coatings and Interfaces (PacSurf 2016) | |
| Thin Films | Wednesday Sessions |
| Session TF-WeP |
| Session: | Thin Films Posters Session II |
| Presenter: | Tomonari Furuya, Hosei University, Japan |
| Authors: | T. Furuya, Hosei University, Japan T. Matsumura, TOSHIBA Corporation, Japan K. Kikuchi, Hosei University, Japan K. Ishibashi, COMET Inc., Japan S. Suzuki, COMET Inc., Japan Y. Yamamoto, Hosei University, Japan |
| Correspondent: | Click to Email |
Chemical states and electrical properties of the CeO2 based compound oxide doped with SiO2 as the promising gate stuck material for MOS devices were investigated, based on the consideration that the crystallization could be suppressed by mixing materials having different crystalline structures. The X-ray photoelectron spectroscopy (XPS) analysis revealed that the compound oxide was successfully prepared on p-type Si (100) substrates by pyrolytic MOCVD using Ce(OCEt2Me)4 at the substrate temperature of 350 °C for 30 min with the intermittent introduction of TEOS (TetraEthoxyOrthoSilicate) for 10 sec every 3, 5, or 10 min. The decomposition temperature of TEOS was lowered by the hydrolysis utilizing H2O generated from Ce source decomposition. In the X-ray diffraction (XRD) patterns, the pure CeO2 films represented the distinct cubic CeO2 peaks, while CeO2 peaks decreased to the trace level for the samples with TEOS introduction; the CeO2 films with TEOS introduction were essentially amorphous.
From the X-ray photoelectron spectroscopy (XPS) spectra of Ce3d, Si2s and O1s, the average molar concentrations of SiO2 in the films with the introduction of TEOS for 10 sec every 3, 5, or 10 min were determined to be 15%, 6% and 6%, respectively. Although TEOS was intermittently introduced during CeO2 deposition, the distribution of Si in CeO2 films was uniform and the amount of incorporated Si was not directly related to the TEOS supply rate. Cerium silicate formation in the film prepared with TEOS introduction was confirmed from Si2s peaks at 153.5 eV and O1s spectra appearing with the shoulder at the higher binding energy.
The electrical properties after annealing at 500°C for 30 min in the ambient of O2 were analyzed by I-V and C-V measurements using the Pt dot electrodes. The sample with TEOS introduction for 10 sec every 3 min represented the lowest leakage current around 1.0×10-5 A/cm2 at 1.5 MV/cm, which was one order of magnitude lower than that of the pure CeO2 films. The relative dielectric constant ranged between 16.6 and 21.6 depending on the TEOS introduction interval. These values were rather higher than that of pure CeO2 films without Si doping which was usually lower than that of bulk relative dielectric constant of 26. These results suggest that Si doping brought about the change in the interface structure between Si substrates and deposited films such as the disappearance of the interfacial layer with lower dielectric constant. The flat band voltage shifted toward lower gate voltages for the samples prepared with TEOS introduction probably due to the introduction of fixed positive charge by silicate formation.