Pacific Rim Symposium on Surfaces, Coatings and Interfaces (PacSurf 2016)
    Thin Films Tuesday Sessions
       Session TF-TuM

Paper TF-TuM9
Optimization of the ZnO Passivation Process on p-type In0.53Ga0.47As Using Atomic Layer Deposition

Tuesday, December 13, 2016, 10:40 am, Room Makai

Session: Nanostructured Surfaces & Thin Films II
Presenter: Changmin Lee, Sungkyunkwan University, Republic of Korea
Authors: C. Lee, Sungkyunkwan University, Republic of Korea
Y. An, Sungkyunkwan University, Republic of Korea
S. Choi, Sungkyunkwan University, Republic of Korea
J. Song, Sungkyunkwan University, Republic of Korea
Y.-C. Byun, University of Texas at Dallas, USA
J. Kim, University of Texas at Dallas, USA
H.S. Kim, Sungkyunkwan University, Republic of Korea
Correspondent: Click to Email

For the performance enhancement of the inversion-type III-V metal-oxide-semiconductor field-effect transistors (MOSFETS), it is essential to improve the interface quality between the high-k gate dielectric and the p-type III-V substrate. Recently, ZnO passivation using an atomic layer deposition (ALD) process was reported to be effective in removing the interface oxides and improving the electrical properties on both p-type GaAs [1] and p-type In0.53Ga0.47As [2].

In this study, the ALD-ZnO treatment was performed on the sulfur-passivated p-type In0.53Ga0.47As substrates with different numbers of cycles at 150 °C. According to the electrical measurement of the MOS capacitors with HfO2 gate dielectrics (ALD at 200 °C), a minimum capacitance increased with a flat band voltage shift when the number of treatment cycles was increased after an optimal condition. The possible origin for the observed changes in the electrical properties will be discussed based on various characterization results, such as the low temperature C-V measurement and chemical analysis using X-ray photoelectron spectroscopy.

[1] Y.-C. Byun et al., ACS Appl. Mater. Interfaces, 6, 10482 (2014).

[2] A. T. Lucero et al., Electron. Mater. Lett., 11, 769 (2015).