| Pacific Rim Symposium on Surfaces, Coatings and Interfaces (PacSurf 2016) | |
| Nanomaterials | Tuesday Sessions |
| Session NM-TuE |
| Session: | Nanofabrication and Nanodevices II |
| Presenter: | Anindya Nath, George Mason University, USA |
| Authors: | A. Nath, George Mason University, USA B.D. Kong, US Naval Research Laboratory, USA A. Koehler, US Naval Research Laboratory, USA V.R. Anderson, U.S. Naval Research Laboratory, USA V.D. Wheeler, US Naval Research Laboratory, USA E.R. Cleveland, US Naval Research Laboratory,USA A.K. Boyd, US Naval Research Laboratory, USA K.M. Daniels, US Naval Research Laboratory, USA R.L. Myers-Ward, US Naval Research Laboratory, USA D.K. Gaskill, US Naval Research Laboratory, USA K.D. Hobart, US Naval Research Laboratory, USA F.J. Kub, US Naval Research Laboratory, USA G.G. Jernigan, US Naval Research Laboratory, USA |
| Correspondent: | Click to Email |
The graphene gold rush for electronic applications has been subdued due to the lack of an energy-gap in the graphene band structure which impedes utilization of graphene-based lateral field effect transistors for switching applications. Alternatively, graphene based vertical devices, such as hot electron transistors (GHETs), have been proposed to overcome the band-gap bottle neck. HETs utilize high energy tunneling injected electrons (hot electrons) to achieve high performance. High on-off ratio can be achieved by biasing the emitter-base and collector-base junctions. For traditional metal-based HETs, the cut-off frequency are limited by base transit time (for thick base metal) or high RC delay (for thin base metal). Graphene offers the ideal solution for HETs due to its ultimate thinness and high conductivity. Epitaxial graphene grown on conducting SiC is an attractive choice for GHETs due to the naturally occurring Schottky barrier between SiC-graphene interface, which can be exploited as the collector barrier. The integration of an emitter-base junction dielectric, however, possess significant challenges due to the low wettability of the graphene sp2 structures. Previous efforts to integrate ultra-thin dielectric layer often lead to metal rich seed layers with pinholes, graphene lattice damage, restricted ALD growth temperature or the inability of wafer scale process integration.
In this work, the amphiphilic nature of graphene oxide is exploited as a seed layer to facilitate ultrathin and conformal high-κ metal oxide deposition on epitaxial graphene by atomic layer deposition at growth temperatures as high as 300°C. Three different high-κ metal oxides (Al2O3, HfO2 and TiO2) with various thicknesses (4 -20 nm) were grown on ultrathin (1.5 nm) GO seed layers on EG. The uniformity and stoichiometry of the films were confirmed by atomic force microscopy and X-ray photoelectron spectroscopy. Additionally, metal-insulator-graphene tunnel devices were fabricated and temperature dependant tunneling behavior is studied. No defect/trap assisted conduction behavior was observed, and a transition from direct to fowler-nordheim tunneling was observed at low temperatures. For graphene field effect transistors (GFETs) with metal oxide on GO seed layer demonstrated high on-state current, low gate leakage current and good channel modulation. Capacitance voltage measurement of the GFETs exhibited low hysteresis and nearly ideal dielectric constants for respective dielectrics. These results demonstrate a simple yet cost-effective universal way of wafer-scale ultrathin high-κ dielectrics deposition on epitaxial graphene by ALD.