AVS 62nd International Symposium & Exhibition
    Energy Frontiers Focus Topic Tuesday Sessions
       Session EN+EM+NS+SE+SS+TF-TuA

Paper EN+EM+NS+SE+SS+TF-TuA9
Porous Silicon Electrochemical Capacitor Devices for Integrated On-Chip Energy Storage

Tuesday, October 20, 2015, 5:00 pm, Room 211B

Session: Batteries and Supercapacitors
Presenter: Donald Gardner, Intel Corp
Authors: D.S. Gardner, Intel Corp
C.W. Holzwarth III, Intel Corp
Y. Liu, Intel Corp
S. Clendenning, Intel Corp
W. Jin, Intel Corp
B.K. Moon, Intel Corp
Z. Chen, Intel Corp
E.C. Hannah, Intel Corp
T.V. Aldridge, Intel Corp
C.P. Wang, Florida International University
C. Chen, Florida International University
J.L. Gustafson, Intel Corp
Correspondent: Click to Email

Integrated on-chip energy storage is increasingly important in the fields of internet of things (IoT), energy harvesting, and sensing. Silicon is already the materials of choice for the integrated circuits found in every IoT device; however, the efforts to integrate electrochemical (EC) capacitors on a silicon die have been limited. Unlike batteries, EC capacitors are electrostatic devices and do not rely on chemical reactions enabling cycle lifetimes of >1M. This is especially important for off-power-grid IoT devices where difficulty associated with regularly replacing the batteries of billions of devices is prohibitive. This work demonstrates electrochemical capacitors fabricated using porous Si nanostructures with extremely high surface-to-volume ratios and an electrolyte. Devices were fabricated with tapered channels sized from 100 nm at the top to 20 nm and with aspect ratios greater than 100:1. Surface coatings were necessary for long-term stability because unpassivated silicon structures react with the electrolytes. To obtain uniform coatings using stop-flow atomic layer deposition (ALD), efficient surface reactions are needed between high volatility, low molecular weight, small molecular diameter precursors without chemical vapor deposition side reactions. TiCl4 and NH3 precursors were found to coat porous Si with TiN uniformly. Measurements of coated P-Si capacitors reveal that an areal capacitance of up to 6 mF/cm2 can be achieved using 2 μm deep pores, and scales linearly with depth with 28 mF/cm2 measured for 12 μm deep pores. Three-terminal CV measurements with EMI-BF4 ionic electrolyte were used to examine the stability of different pore sizes and TiN coating thicknesses. Pores with an average 50 nm width and 100:1 aspect ratio were stable to ±1.2 V when cycled at 10 mV/s and stable to ±1.0 V when cycled at 1 mV/s. Different ionic liquids were studied to determine the ionic liquid best suited to TiN coated porous Si including TEA-BF4/AN, EMI-BF4, EMI-Tf, and a 3M EMI-BF4/propylene carbonate (PC) mixture. Using impedance spectroscopy, the time constant for a 2 μm deep porous Si EC capacitor with a high conductivity TiN coating was found to be 17.6 ms which is fast enough that this can be used for applications involving AC filtering for AC-DC conversion. Measurements of volumetric energy density versus power density of porous Si devices versus other devices show several orders of magnitude higher energy density than electrolytic capacitors with a similar voltage range. These results are also between one to two orders of magnitude higher than other studies utilizing porous silicon and are comparable to commercial carbon-based EC capacitors.