| AVS 62nd International Symposium & Exhibition | |
| Electronic Materials and Processing | Wednesday Sessions |
| Session EM-WeA |
| Session: | Interconnects: Methods and Materials for Removing Connectivity Constraints |
| Presenter: | Jeffery Bielefeld, Intel Corporation |
| Authors: | J.D. Bielefeld, Intel Corporation J. Blackwell, Intel Corporation S. Bojarski, Intel Corporation M. Chandhok, Intel Corporation J. Clarke, Intel Corporation C. Jezewski, Intel Corporation N. Kabir, Intel Corporation S.W. King, Intel Corporation M. Krysak, Intel Corporation D.J. Michalak, Intel Corporation M. Moinpour, Intel Corporation A. Myers, Intel Corporation J. Plombon, Intel Corporation M. Reshotko, Intel Corporation K. Singh, Intel Corporation J. Torres, Intel Corporation R. Turkot, Intel Corporation H. Yoo, Intel Corporation |
| Correspondent: | Click to Email |
To enable the continued scaling of interconnect layers for the 10nm node and beyond an increased number of materials and integration challenges will need to be addressed. Historically, interconnect dielectric materials have been broken down into Interlayer Dielectrics (ILDs) and Etch Stop (ES) / Hard Mask (HM) materials. The ILD layer is the major driver in capacitance improvement, while the ES layer enables patterning and acts as a diffusion barrier. In this paper, we will discuss two major challenges: (1) Pathways for the integration of porous low-k ILDs, and (2) Development needs for ES materials to enable improved patterning options.
The industry continues to work on the integration of low-k ILDs, but the momentum to implement these films has slowed in recent years due to the challenges of working with porous thin films. Low-k ILDs (k~2.0) exhibit 40-50% porosity with an interconnected pore network. The increased porosity can lead to damage and increased roughness during patterning, and can allow precursor penetration during the metal barrier deposition. To mitigate the problems of integrating a porous ILD, we have utilized the approach of pore stuffing. In this process, a sacrificial material is infiltrated into the pores of a fully cured ILD. The resultant film is non-porous with increased mechanical properties.
In this paper, we will discuss the challenges of finding a pore stuffing material that can fill the pores of the ILD, remain in place during dual damascene processing and can then be removed from the low-k ILD post metallization and CMP. In addition, we will show how pore stuffing improves trench profiles, and how it prevents metal penetration during barrier deposition. Finally the successful implementation of this process will be demonstrated and integrated capacitance improvement will be presented.
In a classic dual damascene flow, the ES layer is used as a diffusion barrier and as a patterning stop between ILD layers. To enable more advanced patterning and integration schemes, the role of these materials needs to be expanded. Specifically, there may be situations where multiple ES/HM materials are needed and with high etch selectivity to each other (>20:1). Etch selectivity values for typical materials (e.g. nitrides, carbides, amorphous silicon, metal hard masks and carbon hardmasks) are not currently sufficient. Development of new material options, deposition techniques and etch processes are needed. In this paper, we will discuss the current needs for new ES\HM materials and novel etch technology, along with our current progress toward this challenge.