Invited Paper EM-TuM5
Interlayer Tunnel FETs

Tuesday, October 20, 2015, 9:20 am, Room 210E

The scaling limits of conventional silicon based Complementary Metal Oxide Semiconductor (CMOS) devices has triggered a wide range of research in search of potential candidates for beyond CMOS logic devices. We will discuss the operation of vertical interlayer tunnel field effect transistors (ITFETs) using a stacked double bilayer graphene (BLG) and hexagonal boron nitride (hBN) heterostructure as one such potential candidate. The device is fabricated with a sequential pickup transfer method with the edges of the top and bottom BLG flakes being rotationally aligned to roughly 60° for alignment of the K points in the Brillouin zone of the two graphene layers, and using the hBN as the top, interlayer and substrate dielectric. The device shows multiple negative differential resistance (NDR) peaks which can be adjusted through the gate bias. Temperature dependent measurements show that the peak width of the differential conductance slightly broadens and the height somewhat lowered when the temperature is increased, but overall the temperature dependence is weak enough to be indicative of resonant tunneling being the primary mechanism. Through electrostatic calculations, it is shown that the multiple peaks occur when the two conduction bands at the K-point of the top and bottom bilayer graphene become aligned at certain bias conditions. It is also shown that by adjusting the rotational alignment of the bands of the top and bottom BLG through an in-plane magnetic field, the conductance peaks can be broadened or sharpened. As an example of a potential application, by utilizing the NDR characteristic of the device, a one-transistor latch or SRAM operation is demonstrated which operation margin can be adjusted through the gate bias.