| AVS 62nd International Symposium & Exhibition | |
| 2D Materials Focus Topic | Thursday Sessions |
| Session 2D-ThP |
| Session: | 2D Materials Focus Topic Poster Session |
| Presenter: | Aline Pascon, UNICAMP, Brazil |
| Authors: | A.M. Pascon, UNICAMP, Brazil C.C. Silva, University of Campinas, Brazil J.F. Souza, UNICAMP, Brazil L.T. Kubota, University of Campinas, Brazil L.R.C. Fonseca, UNICAMP, Brazil J.A. Diniz, UNICAMP, Brazil |
| Correspondent: | Click to Email |
Since graphene was successful isolated for the first time by microcleaving of graphite [1], this material has attracting a significant attention of all scientific community, mainly due to its outstanding electronic properties, making it an ideal material to replace the silicon in the traditional FETs. However, the implementation of graphene in the development of FETs has two major issues that should be overcome. The first is that graphene obtained from microcleaving or exfoliation of graphite, does not feature like a scalability technique to be employed in the fabrication of arrays of FETs. The second issue is related with the high contact resistance that appears in the interface metal/graphene. In order to replace the silicon by the graphene as a channel material, a suitable contact with electrodes is required. Aiming to overcome the related issues, herein we have addressed the implementation into arrays of FETs by large area of monolayer graphene produced by the CVD process. Furthermore, we evaluated the effects of the replacement of the conventional, non-refractory metallic electrodes such as Ti/Au or Ti/Pd for the refractory metallic electrodes, such as tantalum nitride (TaN) that has a work function similar to graphene reducing the barrier between metal and graphene.
The CVD graphene was grown based on the procedure proposed by Ruoff and coworkers [2]. This graphene film was transferred on FETs where 22 nm TaOx was used as gate dielectric, in just one step, homogenous and free from PMMA residues or other contamination. The Raman spectra obtained from different areas of the graphene displays a typical G peak at 1587 cm-1, free of defects and a 2D peak at 2684 cm-1, indicating a monolayer of graphene [3].
After the transferring process, the graphene was isolated between the source and drain TaN electrodes due to the photolithography step followed by the oxygen plasma etching, to remove the graphene in the outside area, creating a contact with the electrodes, similar to the dielectric gate. All this process was carried out directly on a die of 2.5 cm2 containing four arrays with 300 FETs each. The latter two processes define the active region of the device, where the electronic transport will occur through the graphene monolayer.
Measurements of electrical properties, with transconductance of 3 mS and contact resistance of 3 kΩ indicate that our devices can achieve high performance, while allows fabricating a massive number of FET-Graphene devices through a simple, fast and scalable approach.
References
[1] K. S. Novolselov et al, Science , 666 (2004).
[2] Xuesong Li, et al., Science 324, 1312 (2009).
[3] A. C. Ferrari et al., PRL 97, 187401 (2006) .