AVS 61st International Symposium & Exhibition
    Electronic Materials and Processing Tuesday Sessions
       Session EM-TuP

Paper EM-TuP24
Low Temperature Growth of High-Quality SiO2 Gate Dielectric by Atomic Layer Deposition

Tuesday, November 11, 2014, 6:30 pm, Room Hall D

Session: Electronic Materials and Processing Poster Session
Presenter: Sangram Pradhan, Norfolk State University
Authors: S. Pradhan, Norfolk State University
E. Tyani, Norfolk State University
A.K. Pradhan, Norfolk State University
Correspondent: Click to Email

A novel as well as simple method preparation of atomic layer deposited high quality SiO2 gate dielectrics were fabricated using highly reactive ozone and tris (dimethylamino) silane. Small frequency dispersion and hysteresis behavior of SiO2 MOS capacitor shows an ideal C-V behavior, suggesting excellent interfacial quality as well as purity of SiO2 film. The flat-band voltage of the samples shifted from negative to positive sweep voltage region with increase in TDMAS pulse from 0.2 to 2 seconds. Based on EOT point-of-view, the ALD SiO2 has gate leakage current density as well as electrical fields of all ALD SiO2 samples are nearly very good and more than (∼10MV/m) which is better comparable to that of thermal silicon oxide grown at temperatures above 800oC. The appealing electrical properties of thin ALD SiO2 enable its potential applications as high-quality gate insulators for thin-film MOS transistors, and insulators for sensor structures and nanostructures on non-silicon substrates.