Paper PS2-TuA8
Sub-22nm Node Mask Patterning for Deep Silicon Trench Etch

Tuesday, October 29, 2013, 4:20 pm, Room 104 C

The fabrication of ever smaller feature sizes at increasing density has driven more stringent requirements on photolithographic processes and patterning schemes. In the sub-22nm DRAM technology, the fabrication of deep silicon memory cells at aspect ratios greater than 30 ratio (depth> 3um: critical dimension < 0.1um) is enabled by a complex mask assembly. In this paper, we will discuss RIE process development for patterning the mask assembly as well as the high aspect ratio Si trenches. The mask assembly comprises of a photo resist layer, silicon anti-reflective coating, organic planarizing layer, oxide layer, and nitride layer deposited on top of a Silicon-on-Insulator (SOI) substrate. Achieving a vertical profile along the trench and across different material types of the mask, while still maintaining the required critical dimension, are major challenges in patterning the mask assembly. The verticality of the different layers in the mask assembly is key because it subsequently affects the deep Si etch process. We will discuss the challenges in achieving high aspect ratio Si trench and key process parameters that influence its dimensions. The paper also describes the capabilities of a commercially available Capacitively Coupled Plasma reactor to meet the requirements of these advanced complex film stacks.

This work was performed by the Research and Development team at TEL Technology Center America in joint development with IBM Semiconductor Research and Development teams in Albany & Hopewell Junction, NY