Paper EM-ThA2
Effect of Hybrid Cleaning in Mitigating Low-k Damage for Critical BEOL Applications at 20 nm Node and Beyond

Thursday, October 31, 2013, 2:20 pm, Room 102 A

Integration of low-k dielectrics (k ≤ 2.7) into the fabrication of interconnects in integrated circuits has enabled the reduction of RC time delays, opening the path for continued scaling. Typical porous low-k dielectrics are formed by plasma-enhanced chemical vapor deposition and contain a significant amount of Si-CHx groups. For the ubiquitous trench-first metal hard mask dual damascene scheme, etching of the via holes into the low-k dielectric is mostly achieved using a fluorocarbon chemistry, after which a cleaning step is needed for concomitant in-situ removal of etch residues as well as the top organic mask for subsequent underlying trench pattern transfer. The cleaning step can either be reductive (N2, H2 containing feed gas) or oxidative (O2, CO2, CO containing feed gas). Owing to their higher reactivity, mild oxidative chemistries comprised of CO2 feed gas have been the predominant chemistry of choice industry-wide, which minimizes the depletion of –CHx groups known as low-k damage while maintaining reasonable etch rates. However, as the industry moves on to advanced technology nodes (sub 20 nm nodes), even minor damage during the cleaning step becomes highly undesirable due to increased RC delay and diminished reliability. This talk will present the successful mitigation of low-k damage as compared to standard cleaning processes through the use of a novel two-step hybrid cleaning strategy. This two-step hybrid cleaning strategy leverages unique hardware solutions with the reactive ion etching efforts for reducing low-k damage.