| AVS 60th International Symposium and Exhibition | |
| Electronic Materials and Processing | Monday Sessions |
| Session EM-MoA |
| Session: | High-k Gate Oxides for High Mobility Semiconductors II |
| Presenter: | S. Anwar, University of Texas at Dallas |
| Authors: | S. Anwar, University of Texas at Dallas C. Buie, University of Texas at Dallas C.L. Hinkle, University of Texas at Dallas |
| Correspondent: | Click to Email |
Germanium has long been considered as a replacement channel material due to its higher intrinsic hole mobility compared to silicon and its relative compatibility with current CMOS processing. Growth of Ge channel materials on bulk Si would be ideal for minimizing cost and allow for the continued use of current manufacturing tools. Ge grown on Si, however, results in a significant defect density due to the 4.2% lattice mismatch, reducing device performance.
In this work, we study the fabrication of tri-gate Ge MOSFETs, grown by MBE, on Si using Aspect Ratio Trapping (ART) 1,2 to reduce the Ge defect density. ART is a growth technique that allows for the reduction of defects for lattice mismatched materials by trapping the threading dislocations into the sidewalls of patterned nanoscale trenches in which the epitaxial growth takes place. This technique has the added benefit of producing the necessary geometric structure required for highly scaled tri-gate devices, alleviating short channel effects, while simultaneously reducing defect density. The fabrication of high aspect ratio (>2) trenches in SiO2 for epitaxial growth of Ge will be discussed as well as the issues and solutions associated with the inherent non-selectivity of solid-source MBE growth. TEM, SEM, and AFM are employed to characterize the growth quality and assess the various device fabrication steps.
Tri-gate MBE-grown Ge MOSFETs on Si are fabricated using a gate first process. A high-quality Ge interfacial region is obtained by a surface functionalization technique using 50 pre-pulses of DI-H2O in an ALD chamber at 250°C, followed by a 2 nm thick interfacial Al2O3 deposition at 250 °C followed by a forming gas anneal (FGA) at 350 °C.3 The FGA step converts the functionalized surface to a thin layer of GeO2, improving the electrical characteristics of the devices. 2.5 nm of HfO2 is then deposited by ALD followed by a 500 °C post-deposition anneal in N2. 150 nm of reactively sputtered TiN is deposited as the gate metal. Schottky junction source and drain regions are formed by sputtering 20 nm of Pt, capped with TiN, and annealed at 400 °C to form PtGe2.4 A final 350 °C FGA completes the device processing. Detailed electrical characterization, using a suite of techniques, was performed and correlated with the MBE growth and gate stack formation.
This work is sponsored in part by the SRC Global Research Corporation.
1 T. A. Langdo, et al., Appl. Phys. Lett. 76, 3700 (2000).
2 J. Bai, et al., Appl. Phys. Lett. 90, 101902 (2007).
3 S. Swaminathan, et al., J. Appl. Phys. 110, 094105 (2011).
4 R. Li, et al, IEEE EDL, 27, 476 (2006).