| AVS 60th International Symposium and Exhibition | |
| Electronic Materials and Processing | Tuesday Sessions |
| Session EM+PS-TuM |
| Session: | High-k Oxides for MOSFETs and Memory Devices I |
| Presenter: | R. Droopad, Texas State University |
| Correspondent: | Click to Email |
The need to reduce power in CMOS devices is critical to the evolution of the next generation devices as scaling continues. The use of new materials for the gate dielectric, and with the possibility of using III-V semiconductors in the channel, there is additional new challenges to maintaining high on-off ratios. One way to reducing the subthreshold slope in low power MOSFET application is through the use of the negative capacitance of ferroelectric layers as part of the gate dielectric proposed by Salahuddin and Datta [1]. This concept has been demonstrated in a polymer ferroelectric MOSFET device exhibiting a sub-60 mV/decade switching behavior [2]. Capacitance enhancement in crystalline ferroelectric-dielectric bilayer has also been demonstrated using a PZT-STO bilayer [3]. Unlike the present amorphous gate stack, ferroelectric gate materials need to be crystalline for the realization of polarization that is oriented along the growth direction. This presentation will detail the growth of ferroelectric complex oxide gate stacks epitaxially on both Si and III-V heterostructures. Deposition is carried out using MBE with careful control of the interfacial nucleation ensuring that the ferroelectric polarization is in the growth direction.
[1] S. Salahuddin, S. Datta, Nanolett. 8 (2008) 405.
[2] A. Rusu, G.A. Salvatore, D. Jiménez, A.M. Ionescu, IEDM 2010
[3] A.I. Khan , D.Bhowmik, P. Yu, S. J. Kim, X. Q. Pan, R. Ramesh, S. Salahuddin, Appl. Phys. Letts., 99 (2011) 113501