Paper EM+PS-TuM2
RF-PVD Si Capping for CET Decrease in High-h/Metal Gate 14nm FDSOI

Tuesday, October 29, 2013, 8:20 am, Room 101 B

Further miniaturization of CMOS technologies will require low values for Capacitance Equivalent Thickness (CET) of gate dielectrics. Below 28nm node, it becomes more difficult for high-k/metal gate (HKMG) MOSFET to reach low CET without degrading gate leakage. One technique for CET scaling already reported [1-4] is based on oxygen scavenging from the HKMG stack after thermal treatment (drive-in anneal). Unlike other reported CET scaling solutions, oxygen scavenging is a promising approach to extend Hf-based HK dielectrics to future nodes [2].

Scavenging techniques incorporating the scavenging elements such as Hf, La, Ti, Al, and Ta directly within the high-k layers have been proposed by many researchers [2-3]. However, this approach can present several drawbacks such as excessive carrier mobility degradation, leakage current increase and effective work function change by formation of fixed charges and/or interface dipoles [3].

In this study, in-situ RF-PVD Si-cap was deposited on top of metal gate in an Applied Materials Endura chamber. HfO₂ and TiN metal gate were used on 300mm FDSOI wafers, using a gate-first integration scheme in a 14nm process flow. The use of an in-situ Si-cap for achieving CET reduction has already been reported in the literature [4]; but, for the first time in this article, we have evaluated a new RF mode PVD Si-cap process, designed to avoid device degradation due to charging.

Firstly, SIMS and XRD measurements were carried out on blanket wafers containing either 20Å or 100Å thick RF-PVD Si-cap deposited in-situ on sacrificial 35Å TiN layer followed or not by drive-in anneal. SIMS results show that amorphous silicon is oxidized at TiN/Si-cap interface during drive-in anneal by pumping oxygen from TiN and high-k, which reduces CET. We demonstrate that Si-cap deposited by RF-PVD remains amorphous for both studied thicknesses whereas sacrificial 35Å TiN layer crystallizes after drive-in anneal, as indicated by XRD. We believe that oxygen diffusion through TiN is possible by means of the grain boundaries formed in TiN during annealing. Secondly, electrical measurements were obtained on 14nm FDSOI devices. As expected, with TiN capping by RF-PVD Si, we succeed to reduce CET by 1Å (6.25%) in PMOS and 0.5Å (4%) in NMOS with no significant degradation of the gate current leakage, no measurable impact on VT, and no device degradation due to charging.

[1] T. Ando et al.,Proceedings of IEEE IEDM, Washington,DC,USA 2009; pp. 423-426

[2] Takashi Ando, Materials 2012, 5, 478-500

[3] C. Choi et al J. Appl. Phys. 2010, 108, 064107:1-064107:4

[4] L.-Å. Ragnarsson et al, Proceedings of IEEE IEDM, Baltimore, MA,USA 2009; pp. 663-666