AVS 58th Annual International Symposium and Exhibition
    Plasma Science and Technology Division Wednesday Sessions
       Session PS+SS-WeM

Paper PS+SS-WeM1
Investigation of Sidewall Passivation Mechanism in a 'CMOS-compatible' Plasma Etching Process for InP-based Photonic Devices

Wednesday, November 2, 2011, 8:00 am, Room 202

Session: Plasma Surface Interactions (Fundamentals & Applications) I
Presenter: Sophie Bouchoule, CNRS-LPN, France
Authors: S. Bouchoule, CNRS-LPN, France
L. Vallier, CNRS-LTM, France
L. Gatilova, CNRS-LPN, France
G. Patriarche, CNRS-LPN, France
S. Guilet, CNRS-LPN, France
L. Le Gratiet, CNRS-LPN, France
Correspondent: Click to Email

Inductively coupled plasma (ICP) etching of II-V semiconductors is now widely used for the development of high-performance emitters, and various chlorine- or HBr- containing chemistries have been proposed for the patterning of InP-based heterostructures required to reach the NIR region. Smooth and anisotropic etching is generally a key-requirement, but only few studies exist on the understanding of the sidewall passivation mechanisms occurring during the etching of InP and related materials. We have shown for the Cl2-H2 and HBr chemistries [JVSTB 26, 666 (2008)] that a silicon oxide layer acting as a lateral etch-inhibitor can build-up on the etched sidewalls of InP-based heterostructures, when a Si wafer is used as the sample tray. This configuration corresponds to most commercial ICP etch systems having an electrode diameter of 4-in or more, used to etch III-V samples of 2-in or less size. However, this may not be the case for future large surface processing of III-V when the III-V wafer will have the same size as the electrode or when III-V dies bonded onto a 200/300 mm wafer have to be etched, where most of the wafer surface is covered by a protecting layer that is not silicon. This may occur in III-V/Si photonic technologies. We have shown that high-aspect- ratio etching of the photonic patterns via a SiOx sidewall passivation mechanism independent of the electrode surface can be obtained when a Si-containing gas such as SiH4, or SiCl4 added [JVSTB 29, 020601 (2011)]. A more detailed analysis of the plasma has shown that hydrogen may promote the deposition of a Si-rich passivation layer on the sidewalls of the etched patterns. SiOCl sidewall passivation takes place during Si ICP etching using Cl2-HBr-O2 chemistry in CMOS technology. We have therefore investigated SiCl4/Cl2/HBr/O2/Ar plasma for the etching of InP dies in a 300-mm CMOS etching tool. This gas mixture provides the Si,O, and H species required for the build-up of a SiOx passivation layer on the InP sidewalls. We show that the passivation mechanism is enhanced when the HBr concentration is increased in the feed gas. We have performed a local analysis of the passivation layer deposited on the InP sidewalls using EDX spectroscopy coupled to TEM. We show that the nature of the passivation layer can be changed from a-Si or nc-Si to SiO2 depending on the hydrogen and oxygen concentrations in the gas mixture. Finally we demonstrate smooth and anisotropic etching of ridge waveguide and vertical Bragg reflector patterns in the CMOS etching tool.