Invited Paper NS+EM-MoM3
III-V Nanowire MOSFETs

Monday, October 31, 2011, 9:00 am, Room 203

III-V Nanowire transistors are cosidered possible candidates to extend the transistor scaling roadmap. The improved electrostatic control in the cylindrical geometry provides benefits for scaling and the advantageous transport properties of the III-V materials may be used to increase the drive current. Besides heterostructure design may be used to tailor the properties in the transistor channel.

In this talk, we will review some of the efforts made in Lund to realize high-perfromance III-V nanowire transistors using vertical nanowires grown by MOVPE. We will show how bottom-up technologies can be combined with top-down processing to realize nanowire-based RF-devices on Si 2" wafers. We use CV techniques to characterize the properties of the high-k material in vertical nanowire capacitors and compare the data to the 1/f-noise characteristics of scaled transistors to evaluate the influence of the high-k material on the transistor performance. We also show that the transistor channel may be reduced down to a diameter of 15 nm without degradation of the transport properties. Finally, we explore the use of novel materials in the transistor structures as we developed GaSb/InAs heterostructures with excellent Esaki diode characteristics to be used for TFET implementations.