The geometry of semiconductor nanowires (NWs) allows for both vertical and coaxial heterostructures, while only vertical heterostructures can be formed using planar structures. This is especially important for III-nitride NWs because crystallographic directions in which heterostructures are formed largely determine the magnitude of internal electric fields due to polarization. Here we describe a method to control the relative vertical and coaxial growth rates in catalyst-free GaN/AlN NW heterostructures grown on Si(111) substrates by plasma-assisted molecular beam epitaxy*.

 

A growth phase diagram is established relating NW density to substrate temperature and III/V ratio. This diagram reveals a reduction in effective growth rate and an increase in nucleation time caused by GaN decomposition. Using this information, a two-step method is developed to independently control NW density from NW deposition time. To begin we nucleate NWs until a small but appreciable density is reached. If deposition continues under these conditions, density will increase over time until reaching a saturation point. To suppress this increase, substrate temperature is increased upon completion of the initial nucleation time. NWs already nucleated continue to grow, but there is no new nucleation, thus controlling density. Additionally, the change in conditions alters growth kinetics, leading to purely vertical NW growth, which allows for the formation of NWs with arbitrarily large aspect ratios and small diameters (~20 nm). Kinetics that favor coaxial growth are also achieved. A low density, high aspect ratio NW array is prepared using the method described above then material is deposited at a lower substrate temperature. The relative coaxial growth rate increases due to lower Ga ad-atom mobility at the lower substrate temperature. Using this dynamic method, we demonstrate multiple period GaN/AlN (2 nm / 2 nm) superlattices along either the vertical or coaxial NW axis, which exhibit atomically sharp compositional profiles. A coaxial, AlN/GaN resonant tunneling diode structure is presented. Large areas of nanowires are processed for electrical measurements without removing them from the Si(111) substrate. Preliminary electrical measurements are provided for both room temperature and low temperature conditions. This work is supported by the ONR under grant N00014-09-1-1153.

 

* S.D. Carnevale, J. Yang, P.J. Phillips, M.J. Mills,and R.C. Myers. “Three-Dimensional GaN/AIN Nanowire Heterostructures by Separating Nucleation and Growth Processes”. Nano Letters 11, 2, pp. 866-871, Jan. 2011.