| AVS 58th Annual International Symposium and Exhibition | |
| Graphene and Related Materials Focus Topic | Tuesday Sessions |
| Session GR-TuA |
| Session: | Graphene on Dielectrics, Graphene Transfer to Novel Substrates |
| Presenter: | Jack Chan, The Univ. of Texas at Dallas |
| Authors: | J. Chan, The Univ. of Texas at Dallas A. Venugopal, The Univ. of Texas at Dallas A. Pirkle, The Univ. of Texas at Dallas S. McDonnell, The Univ. of Texas at Dallas D. Hinojos, The Univ. of Texas at Dallas C. Magnuson, The Univ. of Texas at Austin R.S. Ruoff, The Univ. of Texas at Austin L. Colombo, Texas Instruments Inc. R.M. Wallace, The Univ. of Texas at Dallas E.M. Vogel, The Univ. of Texas at Dallas |
| Correspondent: | Click to Email |
Graphene grown by chemical vapor deposition (CVD) provides a promising pathway for large area fabrication of graphene field effect transistor (FET). However, the performance of CVD graphene FETs reported to date is poorer than FETs fabricated using exfoliated graphene. CVD graphene FETs often exhibit strong hysteresis accompanied with low mobility, large positive Dirac point (VDirac) and large intrinsic carrier concentration. CVD graphene is exposed to a number of aqueous solutions and deionized water when it is transferred to a device substrate. We find that the large VDirac shift and strong hysteresis observed in CVD graphene FET are largely due to water trapped in the graphene/substrate interface during the transfer process.
In this study, CVD graphene grown on copper is transferred to SiO2 substrates with the following three interfacial conditions: i) normal hydrophilic SiO2, ii) SiO2 with 20nm of Al2O3, and iii) a hydrophobic surface prepared by coating hexamethyldisilazane (HMDS). Device performance, including mobility, VDirac and intrinsic carrier concentration are compared in ambient as well as in vacuum. Gate hysteresis is analyzed by measurement of time-resolved channel resistance at various back-gate bias voltages. We find that the gate hysteresis is partially reduced by transferring the graphene onto a substrate coated with HMDS. Vacuum pump down and low temperature (80 °C) annealing can remove the remaining gate hysteresis and VDirac shift. The resulting hole mobility is 5,420cm2/Vs, which is high compared to most of the CVD graphene mobility values reported in the literature.
As a control experiment, the CVD graphene FET fabricated on untreated SiO2 shows a smaller mobility, a larger VDirac and a stronger hysteresis compared to the HMDS coated sample. Under vacuum the hysteresis is reduced but remains significant. We believe the remaining hysteresis is due to adsorbates trapped at the substrate/graphene interface. A graphene FET prepared on a substrate with an Al2O3 interface shows less hysteresis than the sample fabricated on an untreated SiO2 surface but more than that of the HMDS coated surface. In order to study the influence of water trapped between the graphene and the substrate, water is intentionally replaced by isopropanol at the end of the transfer process before drying. In samples prepared using this method, hysteresis and VDirac point shift are both reduced. These results indicate that efforts to prevent trapping of water molecules at the graphene/substrate interface during the transfer process will improve the performance of CVD graphene FETs.
This work was supported by the NRI SWAN center, ONR, NSF and Sandia's LDRD program.