| AVS 58th Annual International Symposium and Exhibition | |
| Electronic Materials and Processing Division | Monday Sessions |
| Session EM1-MoA |
| Session: | Group III-Nitrides and Hybrid Devices |
| Presenter: | Hyeongnam Kim, The Ohio State University |
| Authors: | H. Kim, The Ohio State University M. Schuette, The Ohio State University W. Lu, The Ohio State University |
| Correspondent: | Click to Email |
GaN-based power devices have been intensively investigated for high power switching applications as well as high power microwave applications. Particularly, high breakdown voltage and high saturation velocity of GaN-based heterostructures facilitate reduction in on-state loss and switching loss compared to currently dominant Si-based power devices. Moreover, normally-off GaN-based power field-effect transistors (FETs) offer their inherent safety, reduced power consumption, and diverse circuit functionality with normally-on ones. Recently, we developed a zero-bias Cl-based dry etching process to thin AlGaN barrier with a minimal damage for enhancement-mode AlGaN/GaN FETs. However, it has been difficult to control gate-recess process for normally-off GaN-based FETs due to strong polarization effects. Namely, 1 nm under- or over-etchings near the critical AlGaN barrier thickness where the channel is pinch-off result in a negative threshold voltage (VT) or a degraded transconductance (Gm), respectively. In this work, we report a methodology to control our Cl-based gate-recess for both positive VT and high Gm,MAX by relating electrical properties of the gate-recessed area before gate metallization to VT and Gm in AlGaN/GaN FETs.
Gate-recessed AlGaN/GaN FETs were fabricated through fast etching with BCl3 and slow etching with Cl2/N2/10%-O2 to thin AlGaN barrier. The slow etching runs under inductively-coupled plasma mode only to minimize the damage. For monitoring purpose, resistance at 0 V (R0V) and drain-to-source current (ID,SAT) at 10 V between source and drain contacts were measured before gate metallization to correlate with VT and Gm after gate metal deposition.
ID-VGS, Gm-VGS, and capacitance-voltage characteristics of gate-recessed FETs with different AlGaN thicknesses by doing Cl2/N2/10%-O2 etching for different times were measured and VT values were extracted by linear extrapolation at Gm,MAX. VT and Gm,MAX were correlated with the monitoring parameters of R0V or ID,SAT. VT and Gm,MAX distributions with R0V or ID,SAT guide us for monitoring as well as design of gate-recess process. For example, a recessed FET showing R0V = 1700 W with 7 nm AlGaN barrier exhibits VT of 0.56 V and Gm,MAX of 300 mS/mm. In addition, our recess process offers sufficiently long monitoring time (at least 4 minutes) to tune the gate recess for target VT together with high Gm,MAX. Based on the distribution, the necessity of tuning process is determined and its progress is monitored by R0V or ID,SAT before gate metallization until target R0V or ID,SAT is met. Our electrically monitoring method allows gate recess process to be well-controlled for target VT and Gm,MAX.