|AVS 57th International Symposium & Exhibition|
|Thin Film||Wednesday Sessions|
|Session:||High K Dielectrics for Si Electronics|
|Presenter:||R. Hendel, Periodic Structures Inc.|
|Correspondent:||Click to Email|
Moore’s Law has been the driver for semiconductor integrated circuits over more than 40 years. Relentless scaling of dimensions switching provided increasing functionality and performance, resulting in leading edge single chips today that incorporate more than 1 Billion transistors.
All attempts on predicting the end of Moore’s Law have been futile – innovations have always allowed continued scaling at reduced cost. However, while Moore’s Law appears to be a continuous curve, we rarely reflect on the underlying changes that had to occur to enable this rate of progress. These changes comprised device architecture, the introduction of new materials and break-through processes.
Since Moore’s Law describes a learning curve for which cost reduction is central, process simplicity frequently won out over performance advantages if the latter came at high cost. Self-aligned implanted poly-gate over the early metal gate structures is a prime example. Aggressive reduction in the cost per function also provided performance benefits: Smaller transistors switched faster and used less power to do so – truly a win-win situation.
Key innovations along this path were:
· The switch from thermal diffusion doping to implant
· The introduction of CMP, which was key in increasing the number of metal layers that could be integrated.
· The introduction of high-k dielectrics in conjunction with metal gates which addressed the critical gate leakage problem and will allow the introduction of new and better performing channel materials.
Compared to the past, the future will require even more innovation along three potential directions:
· Continuous improvements of current methodologies along existing technologies, consisting of solid engineering and hard work.
Innovations pursued in this category are: highly regular layouts, new channel materials in conjunction with modified hi-k/MG (yet planar) structures.
· Significant changes to traditional device structures and processes.
An example of innovations pursued in this category is the FinFET, which presents significant challenges in materials and processes that must be resolved before introduction into the manufacturing cycle.
· Radical new structures and approaches resulting in major deviation from today’s mainstream technologies.
An example is new fundamental circuit components such as the Memristor or new approaches available if considering device operations at cryogenic temperatures (which may be feasible for server farms), allowing the exploration of concepts such as superinsulators.
This presentation will highlight the state-of-the-art in process technology and discuss challenges that require attention and timely solutions.