AVS 57th International Symposium & Exhibition
    Graphene Focus Topic Wednesday Sessions
       Session GR+EM+MS+TF+MI-WeM

Epitaxial Graphene: Effects of Dielectric Overlayers and Device Design on FET Performance

Wednesday, October 20, 2010, 8:00 am, Room Brazos

Session: Graphene and Carbon-based Devices
Presenter: M.J. Hollander, The Pennsylvania State University
Authors: M.J. Hollander, The Pennsylvania State University
R. Cavalero, The Pennsylvania State University
D. Snyder, The Pennsylvania State University
M. LaBella, The Pennsylvania State University
K. Trumbull, The Pennsylvania State University
Z. Hughes, The Pennsylvania State University
J. Robinson, The Pennsylvania State University
Correspondent: Click to Email

The realization of a graphene-based electronic technology necessitates large-area graphene production, as well as the ability to integrate graphene with highly insulating films that act as the gate dielectric in field effect transistors (FETs). Graphene’s two dimensional nature allows for phenomenal electronic properties and ultimate scalability, but also makes it susceptible to doping and scattering by charged impurities, dangling bonds, and other defects that may derive directly from choice in gate dielectric and deposition technique. The nature and extent of the effect of the dielectric over-layer on conduction within the graphene channel is of fundamental interest in designing and producing graphene based FETs. Atomic layer deposition (ALD) has proven to be an excellent technique toward the integration of dielectrics with graphene and provides a means to produce high quality films for gate dielectrics at temperatures below 300C, but requires the use of a thin nucleation layer to promote complete coverage and to protect the graphene.

We present results on graphene FETs utilizing various gate dielectrics and various nucleation layers. Graphene was grown epitaxially on 100 mm SiC wafers and processed using standard photolithographic techniques. Al2O3 and HfO2 gate dielectrics were investigated using SiO2, TiO2, and Al2O3 nucleation layers in various combinations. We show that choice of gate dielectric and nucleation layer can have a dramatic effect on transistor performance and charge carrier mobility. Saturation current, transconductance, and device hysteresis were examined in the fabricated FETs while charge carrier mobility and charge carrier density within the epitaxial graphene were evaluated using Van der Pauw structures. Graphene FETs utilizing Al2O3 and SiO2 seeded dielectrics exhibit the best performance while TiO2 seeded and unseeded devices exhibit large gate leakage currents resulting in non-functioning FETs. Additionally we provide evidence that the choice of dielectric and seed can significantly impact the Dirac point (minimum conduction), amount of hysteresis, and on/off ratio of the graphene FETs. Trends in saturation current, and transconductance appear be independent of nucleation layer and gate dielectric choice, indicating that conduction through the channel may be limited by mechanisms independent of the nucleation layer and gate dielectric.

In addition to the aforementioned performance metrics, FET performance after continued application of high electric fields across the channel will be reported. Finally, we examine how choice of channel length and width, along with transistor design, effect performance.