AVS 56th International Symposium & Exhibition
    Plasma Science and Technology Wednesday Sessions
       Session PS2+MN-WeA

Paper PS2+MN-WeA1
Advanced DRIE Via Etching

Wednesday, November 11, 2009, 2:00 pm, Room B2

Session: High Aspect Ratio and Deep Etching for 3D Integration and Memory
Presenter: F. Gao, VTT Technical Research Centre of Finland
Authors: F. Gao, VTT Technical Research Centre of Finland
D. James, VTT Technical Research Centre of Finland
K. Kolari, VTT Technical Research Centre of Finland
J. Kiihamäki, VTT Technical Research Centre of Finland
M. Muggeridge, Aviza Technology, Inc.
Correspondent: Click to Email

We present 3 different types of interconnection vias fabricated by deep reactive ion etching (DRIE) on silicon substrates. One type of vertical vias with 30µm diameter mask opening are etched through 400µm thick wafer by switched Bosch process, featured by very fast etch rate at about 6µm/min and over 12:1 aspect ratio. The other type of vertical vias are tested on smaller diameters ranging from 1-9µm and etched to 20-50µm deep. Those vias have the minimum undercut and smooth sidewalls achieved by non-switched etching. Another type of tapered vias with 75µm mask opening are etched isotropically in DRIE resulting in over 150µm deep vias with 70-80 degree tapering. Silicon etch selectivity against different mask materials are studied and compared for the vertical vias. Thick resist is thought to be better mask to minimize undercut and via top erosion by reflected ions. Tapered vias have the problem of sidewall roughness from the isotropic etch. Both plasma cleaning and argon annealing methods are tested to smooth the silicon sidewalls in the tapered vias.