Invited Paper MI-ThM3
Racetrack Memory: A Current Controlled Domain Wall Shift Register

Thursday, November 12, 2009, 8:40 am, Room C1

Racetrack Memory¹ promises a novel storage-class memory with the low cost per bit of magnetic disk drives but the high performance and reliability of conventional solid state memories. Unlike conventional memories, the fundamental concept of Racetrack Memory is to store multiple data bits, perhaps as many as 10 to 100, per access point, rather than the typical single bit per transistor. In Racetrack Memory the data is stored in the form of a series of magnetic domain walls along magnetic nanowires which are oriented either parallel or perpendicular to the surface of a silicon wafer. These distinct structures form “horizontal” and “vertical” Racetrack Memories. Conventional CMOS devices and circuits are used to provide for the creation and manipulation of the domain walls in the magnetic nanowires or “racetracks”. The domain walls are shifted back and forth along the nanowires using nano-second long current pulses via the transfer of spin angular momentum from the spin polarized current. Note that the shifting of neighboring domain walls in the same direction along a nanowire is not possible using conventional means of manipulating domain walls with localized magnetic fields.

In this talk we discuss progress towards building a Racetrack Memory and the fundamental physics underlying it. In particular, we discuss the current and field controlled dynamical motion of magnetic domain walls in magnetic nanowires formed from permalloy and related materials.

[1] S.S.P. Parkin, M. Hayashi and L. Thomas, Science 320, 190 (2008); S.S.P. Parkin, Scientific American (June, 2009).