AVS 55th International Symposium & Exhibition
    Nanometer-scale Science and Technology Wednesday Sessions
       Session NS+NC-WeA

Paper NS+NC-WeA5
A Single-Walled Carbon Nanotube Thermal Sensor Integrated with CMOS Circuitry

Wednesday, October 22, 2008, 3:00 pm, Room 311

Session: Nanoscale Devices and Sensors
Presenter: M.R. Dokmeci, Northeastern University
Authors: M.R. Dokmeci, Northeastern University
S. Sonkusale, Tufts University
C.-L. Chen, Northeastern University
V. Agarwal, Tufts University
Correspondent: Click to Email

In this paper we present Single-Walled Carbon Nanotube (SWNT) thermal sensor integrated with CMOS integrated circuits. The chip was fabricated using the AMI 0.5um CMOS Technology. Electrical measurements from the assembled SWNTs yield ohmic behavior with a two-terminal resistance of ~44KOhms. The SWNTs were incorporated on to the CMOS chip as a feedback element of a two-stage Miller compensated high gain operational amplifier. The measured small signal ac gain (~1.95) from the inverting amplifier confirmed the successful integration of carbon nanotubes with the CMOS circuitry. After assembly, the thermal behavior of the CNT-CMOS system yield a TCR value of -0.33 measured through the operational amplifier indicating that the SWNT device has potential applications in temperature sensing. This paper lays the foundation for the realization of next generation integrated nanosystems with CMOS integrated circuits. Recently, numerous approaches for the synthesis and device applications of nanoscale materials such as nanotubes and nanowires are being demonstrated. Despite the exciting preliminary success of nanowire research, one of the limitations is the absence of integration of the nanostructures with CMOS circuitry. The heterogeneous integration of nanostructures with readout electronics not only improves the signal to noise ratio, but also provides a means to record, buffer and amplify the measured signals on the same chip leading to highly sensitive nanostructure based nanosystems. The nanotube-CMOS assembly (based on Dielectrophoresis) utilized electrodes realized from the metal 3 layer of CMOS process and did not require any extra processing steps. SEM imaging results and the I-V measurements both confirm the controlled placement of nanotubes on to the electrodes attached to the CMOS circuitry. The measured ac gain of the operational amplifier (~1.95) matched the calculations well (2). SWNTs have a significant thermal response. The measured gain from the op-amp at 100ºC was ~1.26 which corresponded to a decrease in SWNT resistance. In summary, we have demonstrated a technology for integrating carbon nanotubes on to functional CMOS circuitry. The technique is simple, versatile and high yield with potential applications for the realization of nanotube based bio and chemical sensors fabricated on CMOS electronics.