AVS 54th International Symposium | |
Nanometer-scale Science and Technology | Wednesday Sessions |
Session NS2+EM-WeA |
Session: | Nanoscale Devices and Nanowires II |
Presenter: | G. Zhang, Sungkyunkwan Advanced Institute of Nano-Technology, Korea |
Authors: | G. Zhang, Sungkyunkwan Advanced Institute of Nano-Technology, Korea W.J. Yoo, Sungkyunkwan Advanced Institute of Nano-Technology, Korea |
Correspondent: | Click to Email |
Channel hot electron injection (CHEI) programming is widely used for NOR Flash memory operations, whose efficiency is determined by both hot electron (HE) injection level and electron capture rate in which an electron excitation and relaxation process is involved.1 Inelastic phonon scattering is considered as the main mechanism to cause HE relaxation, where HE energy loss rate decays with larger electron/phonon temperature divergence.2 As a result, electron capture rate of deep traps decays sharply with the increase of HE temperature (Te).3 We consider that phonon scattering occurs actively at interfacial junction of different layers, where regularity of lattice structure is disturbed. In this work, we investigated capture rate dependent CHEI programming efficiency for different junction widths or phonon temperatures (Tp). It is found that HEs are injected into the gate stack as lucky electrons,4 resulting in small capture rate or low programming efficiency; instead, warm electrons (WE), which are generated by thermally enhanced F-N tunneling, play a more important role in programming with higher capture rate. In this work, a practical method to effectively enhance programming speed using extended SixZr1-xO2 interfacial junction between tunnel SiO2 and ZrO2 trapping layer in SONOS type Flash memory is proposed. Cross-sectional TEM image shows that the ZrO2 is highly reactive with SiO2 to form a SixZr1-xO2 interface of graded composition over the thickness of ~2 nm. HfO2 has a similar band structure with ZrO2 but a thinner (0.5~0.7nm) interface and Si3N4 has a smaller conduction band energy offset to SiO2. We observed effectively enhanced programming efficiency at various operation temperatures for the devices using a charge trap layer of ZrO2, compared to those using Si3N4 by ~3.2 times and HfO2 by ~2.2 times. Furthermore, ZrO2 demonstrates clear advantages in low-voltage operation and large Vth window over Si3N4 and HfO2, being a very attractive material contender for next-generation NOR Flash application.
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2W. Cai, et. al., Physical Review B, p8573, 1986.
3R. Passler, Solid-State Electronics, p155, 1984.
4S. Tam, et. al., IEEE Trans. Electron Devices.,vol.31, n.9, p1116, 1984.