AVS 51st International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS2-MoM

Paper PS2-MoM6
Silicon Recess Formation During High Density Plasma Polysilicon Gate Etching

Monday, November 15, 2004, 10:00 am, Room 213B

Session: Silicon Etching
Presenter: S.A. Vitale, Texas Instruments
Authors: S.A. Vitale, Texas Instruments
B.A. Smith, Texas Instruments
Correspondent: Click to Email
Silicon loss during gate etch from the active region of a traditional CMOS transistor is shown to take place through plasma oxidation of the silicon substrate during the over-etch step. The plasma oxidation occurs by an ion-enhanced process with an activation energy of only 0.02 eV. This phenomenon is successfully modeled using the traditional Deal-Grove thermal oxidation model, with the inclusion of a depth-dependent reaction rate constant to incorporate the ion-enhancement effect. Plasma oxidation and silicon loss are reduced by using a shorter poly over-etch time, lower source and bias power, lower substrate temperature, and lower O2 flow. A viable poly-over etch process was developed which produced vertical poly profiles while reducing the silicon loss by 32%.