AVS 51st International Symposium
    Plasma Science and Technology Tuesday Sessions
       Session PS1-TuM

Paper PS1-TuM2
Reduction of Line Edge Roughness for 90nm Technology Node for Contact and Trench Etched Features

Tuesday, November 16, 2004, 8:40 am, Room 213A

Session: Dielectric Etching
Presenter: D. Farber, Texas Instruments
Authors: D. Farber, Texas Instruments
W. Dostalik, Texas Instruments
B. Goodlin, Texas Instruments
R. Kraft, Texas Instruments
T. Lii, Texas Instruments
Correspondent: Click to Email
For the 90nm technology node, methods for reducing line edge roughness (LER) during dielectric etch are shown. Two particular, distinct cases are demonstrated here: 1) contact holes etched in phosphorus-doped glass (PSG), and 2) trench lines in organo-silicate glass (OSG) low-K dielectric for damascene Cu interconnect. For both cases, an etch strategy is developed to deal with the inherent roughness and granularity of 193nm photoresist while maintaining adequate CD control and resist thickness margin. Using an image processing technique, an effort is made to quantify the degree of LER associated with the processes.