AVS 51st International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS1-MoM

Paper PS1-MoM8
Comparison of In-situ and Ex-situ Resist Strip Process for Ultra Low-k/ Cu Interconnect

Monday, November 15, 2004, 10:40 am, Room 213A

Session: Low-k Dielectric Etching
Presenter: H. Xu, ULVAC Technologies
Authors: H. Xu, ULVAC Technologies
A. Shen, ULVAC Technologies
V. Tarasov, ULVAC Technologies
B. White, International Sematech
J. Wolf, International Sematech
Correspondent: Click to Email
According to the ITRS roadmap, ILD layer with effective dielectric constant (k@sub eff@) of < 2.7 will be needed for 65 um technology node for high performance logic devices. To achieve k@sub eff@ of < 2.7, ultra low-k film with bulk k of < 2.1 will be needed. One of the challenges in integrating the ultra low-k material is the susceptibility of low-k material to damage from the post etch resist ashing and residue clean process. Directional resist ashing at low wafer temperature may provide a solution for avoiding damage to ultra low-k materials. Directional resist ashing can be done either in situ in a low-k etch chamber or ex situ in a standalone ash chamber. In this paper we will compare the process results between in situ and ex situ resist ash for ultra low-k film. The N@sub 2@/H@sub 2@ in situ ashing was done in a low k etch chamber which is a magnetically enhanced RIE reactor. The O@sub 2@ based ex situ ashing was done in a plasma chamber on an asher platform. This chamber incorporates a WCP plasma source and an independent wafer RF bias for independent plasma density and ion energy control. The WCP source was an ULVAC designed inductively coupled plasma source for achieving higher plasma density and lower electron temperature than a conventional ICP source. One experiment with an N@sub 2@/H@sub 2@ chemistry shows that while both in situ and ex situ resist ash shows comparable RC products. The RC product is an indirect measure of k@sub eff@, obtained from serpentine and comb test structure of 0.125/0.175um line width/spacing, indicating equally low damage to the ultra low-k film by the ash process. The ex situ N@sub 2@/H@sub 2@ ash process caused much less corner rounding of the SiC cap layer . Another experiment using a dilute O@sub 2@ ash process, shows that the RC product is sensitive to the chamber conditions used for resist ashing, suggesting mixing low k etch with O@sub 2@ based resist ash in the same chamber may cause more damage to ultra low-k film.