AVS 51st International Symposium
    Plasma Science and Technology Friday Sessions
       Session PS1+DI-FrM

Paper PS1+DI-FrM6
Etching of HfO@sub 2@ and HfSiO@sub x@ at Elevated Temperatures

Friday, November 19, 2004, 10:00 am, Room 213A

Session: High K and Difficult Materials Etch
Presenter: M. Hélot, CNRS, France
Authors: M. Hélot, CNRS, France
G. Borvon, LTM-CNRS, France
T. Chevolleau, LTM-CNRS, France
L. Vallier, LTM-CNRS, France
O. Joubert, LTM-CNRS, France
P. Mangiagalli, Applied Materials
J. Jin, Applied Materials
Y.D. Du, Applied Materials
M. Shen, Applied Materials
Correspondent: Click to Email
In CMOS technology, the traditional SiO@sub 2@ used as gate dielectric is being replaced by a material presenting a higher dielectric constant (so called high-K materials) for the 65 or more likely the 45 nm nodes. In the integration of such materials, the etch process is one of key issues since the volatility of etch by-products is low and the high-K/Si selectivity seems extremely difficult to achieve. This work is dedicated to the etching of HfO@sub 2@ and HfSiO@sub x@, two of the most promising candidates, using an industrial inductively coupled plasma source (ICP) with a hot cathode (the temperature range of the wafer can be adjusted from 200 to 350°C). Vertical high-K profile without footing or silicon recessing have been achieved. AFM measurements of silicon surface show an acceptable substrate roughness after etch. The etch process has to be adjusted with respect to the deposition technique (CVD vs. ALD) as well the thickness of the silicon oxide buffer layer between the silicon substrate and the high-K layer. XPS analyses reveal that the selectivity is obtained thanks to the formation of a thick C and Cl overlayer on SiO@sub 2@ and not on HfO@sub 2@. Even for these very thin layers, the endpoint techniques such as emission spectroscopy and spectroscopic ellipsometry have to used. Finally we found that the etch process (etch rate and uniformity) depends on the walls reactor seasoning.