AVS 51st International Symposium
    Plasma Science and Technology Tuesday Sessions
       Session PS+MS-TuA

Paper PS+MS-TuA1
Preliminary Investigations for Ultimate Gate Patterning

Tuesday, November 16, 2004, 1:20 pm, Room 213A

Session: 45nm Node with Panel Discussion
Presenter: J. Foucher, CEA-LETI, France
Authors: E. Pargon, LTM-CNRS, France
J. Foucher, CEA-LETI, France
J. Thiault, LTM-CNRS, France
O. Joubert, LTM-CNRS, France
Correspondent: Click to Email
The fabrication of a sub-20nm transistor gate requires a very accurate control and understanding of all the plasma steps (resist trimming, BARC, hard mask open and gate etch) involved in the gate stack processes. Then, it is important to study the parameters that can generate a deviation of the final gate dimension for each of these plasma steps. The two aspects that we have studied are the etching behaviour of the photoresist mask exposed to the plasma, and the chemical nature of the layers that deposit on the reactor walls and feature sidewalls during the process. We have developed an experimental procedure using XPS analyses to characterize the chemical modifications occurring on the tops and sidewalls of the photoresist mask as well as the chemical nature of the coatings formed on the chamber walls. These analyses can be correlated with the process performances (in terms of etch profile and critical dimension control (CD control). SEM observations and CD AFM 3D have been used to get the process performance. In all the plasma conditions investigated, the BARC and hard mask opening steps both lead to a CD deviation of 5 to 15 nm attributed to the modifications of the photoresist mask during plasma exposure. XPS analyses and 3D AFM measurements show that the passivation layers formed on the pattern sidewalls during the gate etch step itself are strongly influenced by the pattern density and etch chemistry. Finally, we show that the only way to control gate etch processes in the sub 20 nm range is to minimize strongly the formation of the passivation layers on the gate sidewalls.