AVS 51st International Symposium
    MEMS and NEMS Monday Sessions
       Session MN-MoP

Paper MN-MoP12
Process Integration for Through-Silicon Vias

Monday, November 15, 2004, 5:00 pm, Room Exhibit Hall B

Session: Poster Session
Presenter: Z. Rahman, University of Arkansas
Authors: S. Burkett, University of Arkansas
L. Schaper, University of Arkansas
Z. Rahman, University of Arkansas
G. Vangara, University of Arkansas
S. Spiesshoefer, University of Arkansas
S. Polamreddy, University of Arkansas
Correspondent: Click to Email
Development of an integrated process flow for the fabrication of Cu filled vias in silicon will be described. The formation of a through-silicon via (TSV) enables three-dimensional (3-D) interconnects for chip-stacking applications that will be especially important for integrating heterogeneous devices. A strong motivation for 3-D interconnects is the much reduced time delay that will be observed by connecting chips at the via or interconnect level rather than through conventional metallic wiring. The formation of a TSV involves many processing steps with the major areas including: via formation; deposition of via insulation, barrier, and Cu seed films; Cu electroplating for via-fill; wafer thinning; and backside processing. The via diameter is 4-8 @micron@, via depth is 15-20 @micron@, and a 20 @micron@ pitch is used in this study. Vias formed at these dimensions will result in a high interconnect density. A primary challenge to implementation of 3-D stacking is the process integration involved in TSV technology. A major requirement is that the techniques in the integrated process flow are chemically, mechanically, and thermally compatible. Vias are formed by both conventional reactive ion etching (RIE) and by the Bosch process using deep RIE (DRIE). These processes will be compared. The via profile that is obtained determines the step coverage that will be achieved in the subsequent thin film deposition steps. SiO@sub2@ deposited by PECVD forms the via lining; sputtered TaN and Cu provide barrier and seed films, respectively. A fountain Cu reverse pulse electroplating method is used to fully fill the vias. A carrier wafer is required at this point for handling thin wafers. Wafer bonding of this carrier wafer involves a lamination process and wafer thinning involves mechanical grinding, chemical spray etching, and a blanket etch to open the vias. Each step will be described in the process flow with the considerations discussed for successful process integration.