AVS 51st International Symposium
    Applied Surface Science Monday Sessions
       Session AS-MoP

Paper AS-MoP23
Scanning Capacitance Microscopy Study on the Stability of the Electrical Junctions Formed by Spike Annealing and Rapid Thermal Annealing

Monday, November 15, 2004, 5:00 pm, Room Exhibit Hall B

Session: Poster Session
Presenter: M.-N. Chang, National Nano Device Laboratories, Taiwan
Authors: M.-N. Chang, National Nano Device Laboratories, Taiwan
C.-Y. Chen, National Nano Device Laboratories, Taiwan
Correspondent: Click to Email
Scanning capacitance microscopy (SCM) has been widely used to profile two-dimensional carrier distribution and examine the electrical junctions of silicon-based devices. Ion implantation combined with proper annealing treatments is indispensable to produce a needed electrical junction. In general, the annealing treatments can be rapid thermal annealing (RTA) or spike annealing (SA) at high temperature. Due to the photoperturbation effects on SCM, there are many difficulties in employing SCM to investigate the temperature influence on electrical junctions. In this work, we have provided a reliable method to control the photoperturbation levels on the studied samples and employed low-photoperturbed SCM, operated under the same photoperturbation levels, to study the stability of the electrical junctions formed by RTA and SA. Studied samples were p@super +@/n junctions formed by BF@sub 2@@super +@ implantation at low energies. RTA and SA processes were performed at 1050 °C in N@sub 2@ ambient. The width and pitch of the designed grating pattern are 0.8 and 2 @micro@m, respectively. The differential capacitance images clearly show that post-SA and -RTA furnace annealing at low temperatures can induce the electrical junction narrowing. With secondary ion mass spectroscopy, it is further revealed that the junction narrowing may occur even if atomic diffusion is negligible. The experimental results indicate that point defect generation/recombination associated with dopant deactivation plays an important role of junction width modification during the following low temperature processes. According to this study, the electrical junction formed by high temperature annealing is unstable. The physical mechanism of junction width variation induced by low temperature processes will be discussed in depth.