Paper NM-TuP9
Electrical Properties of Vertically Integrated Thin Film Transistors using Amorphous-In₂Ga₂ZnO₇ Channel Layer

Tuesday, December 9, 2014, 4:00 pm, Room Mauka

Recently, serially connected transistors with vertical configuration have received considerable attention in memory applications due to their potential to increase integration density to ultra-high values. In transistors with the vertically integrated configuration, the semiconductor channel material is usually composed of polycrystalline Si (poly-Si). Although the poly-Si channel has revealed feasible functionality as the semiconductor channel, degraded mobility, uniformity and reliability concerns related to the presence of grain-boundaries have not yet been completely resolved. In this regard, the amorphous nature and high carrier mobility of In₂Ga₂ZnO₇ (a-IGZO) thin films attract a great deal of attention as the channel material for such applications.

In this study, two serially connected and vertically integrated a-IGZO thin film transistors (V-TFTs) were fabricated using a gate-first fabrication process. The V-TFTs were fabricated with a vertical channel length (L_g) of ~500 nm for the top TFT (t-TFT) and ~400 nm for the bottom TFT (b-TFT). Heavily doped p-type silicon was used as the substrate and gate of b-TFT (G_b). A 100-nm-thick SiO₂ layer was thermally grown as the isolation layer between the t- and b-TFTs. 500-nm-thick poly-Si was deposited by low-pressure chemical vapor deposition to make the gate of the t-TFT (G_t). Then, the poly-Si/SiO₂/Si structure was dry etched sequentially to form the gates. Then, a 100-nm-thick SiO₂ layer was deposited by a PECVD as the gate dielectric layer, and an a-IGZO layer was sputter-deposited at room temperature on this structure with a target thickness of 100 nm on the top surface of the sample, which results in a channel thickness of ~40 nm for the t-TFT, and ~50 nm for the b-TFT on the side walls of the SiO₂. Finally, the Ti source and drain contacts were fabricated by a lift-off process, as the Ti contact with the a-IGZO is quasi-Ohmic.

The t- and b-TFTs show well-behaved transfer characteristics, with an I_on/I_off ratio (~ 10⁸) and an SS value of 0.6 V/dec., which are much improved device parameters compared with the previously reported single-layer V-TFT, for which the gate-last fabrication process was adopted. This is due to the favorable distribution of the electric field by the V_d and V_g of the TFTs, where the influence of V_d on the channel can be minimized compared with that from V_g. While the two serially connected TFTs behave well and rather independently of each other, there were certain cross-influence between them. Details for such cross-talk will be discussed in the presentation. Further study results up to four layer V-TFT will also be presented.