Harnessing Chemistry to Deliver Materials and Process for the Next 10 Years of CMOS Evolution
Friday, April 15, 2016
11:00 am, NSERL 3.204
Speaker: Dr. Robert Clark, TEL Technology Center, America, LLC.
The AVS Dallas Metroplex Student Chapter is proud to have the opportunity to host Dr. Robert Clark,
of TEL Technology Center, America, LLC.as our guest speaker. Dr. Clark has an impressive industry career,
working at the interface of chemistry and semiconductor devices.He will also meet with the AVS for an informal
career talk and Q&A session on Friday afternoon @ 2:00PM in NSERL 3.744.
Pastries and refreshments will be provided.
ABSTRACT:
The continued scaling of the Integrated Circuits (ICs) according to Moore’s law has led to a doubling of the number of devices
per unit area in semiconductor microchips approximately every 2 years since 1962.1 Over the past decade traditional scaling
by simple linear shrinking has effectively ceased as IC makers have adopted new 3-dimensional device structures, complex
integration schemes and new processes and materials for an expanding number of applications in order to overcome
fundamental physical limits.2 The use of atomic layer deposition (ALD) for the deposition of High K dielectrics during
replacement gate FinFET fabrication is but one example of this new paradigm. In order to continue Moore’s law in the coming
decade this trend will not only continue, but accelerate as devices are scaled to a level approaching atomic dimensions.
Broadly speaking, two major trends are influencing the development of future IC manufacturing processes: the need to
harness the third dimension to extend Moore’s law; and the need for “self-something” processes. “Self-something” processes
refers to processes or schemes that are directed chemically to attain a desired result and includes processes that are selflimited
(e.g. ALD or atomic layer etching), self-directed (e.g. directed self-assembly or selective deposition), or self-aligned (e.g.
self-aligned contacts) in some way that enables device density scaling. “Self-something” processes are required in order to
harness the third dimension and make use of new non-planar device architectures (e.g. FinFETs and stacked DRAM capacitors),
device arrays/stacking (e.g. 3D NAND and cross-point memory), and 3D integration (e.g. monolithic 3D, and chip stacking).
Highly tailored ALD processes are being investigated to fabricate functional material layers for future device architectures.
Interspersed treatments and doping may be used to optimize the resulting physical or electrical properties. Ultra-thin
dielectric and metal layers may be deposited inside of high aspect ratio contact structures and selective deposition processes
can be used to deposit functional materials only where they are needed, thus reducing the patterning burden during IC
manufacturing. Depositing dopant layers by ALD for thermal solid source doping can be used to conformally dope 3-D device
structures without the damage caused by implantation. Examples of these and similar processes will be described and
discussed along with the chemical processes and transformations governing film deposition, composition, structure, and
interface control. These processes, and others like them, provide the technological basis for extending Moore’s law at least
through the next decade.
BIO:
Robert Clark received his Ph.D. in Chemistry in 2000 from U.C. Irvine and holds B.S. and M.S. Chemistry degrees from Virginia
Tech. He joined Air Products and Chemicals in 2000 where he worked as a Principal Research Chemist developing ALD High K
and Metal Gate precursors including the first ALD High K Gate Dielectric precursor used in high volume manufacturing. In 2006
he Joined Tokyo Electron at the TEL Technology Center, America (TTCA), LLC in Albany, New York and relocated to California in
2010. He is currently an elected Senior Member of the Technical Staff for Tokyo Electron U.S. His research spans FEOL and
BEOL integration and devices including advanced device integration, ALD, CVD, patterning, functional patterning/integration
films, selective depositions, ALE, advanced cleans, surface preparations, FinFETs, Nanowire FETs, High K/Metal Gate Films,
advanced contacts, alternative channel materials, resistive memories and DRAM. He chaired SRC Device Sciences in 2013 and
is currently on the ITRS Wafer and Environmental Control Committee. He is a member of several conference committees
including SISC, VLSI-TSA, and CMC. He holds more than 35 issued U.S. patents and has authored or co-authored more than 90
publications and conference presentations including numerous invited presentations and papers.